As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
In some situations, information handling resources (e.g., Peripheral Component Interconnect (PCI) or Peripheral Component Interconnect Express (PCIe) devices) may experience electrical instability during exit from a low-power state. Somewhat similarly to when a device is first powered on (or fully reset), a device's exit from a low-power state may cause signals to transition from power logic 0 to power logic 1. As currents rush through electrical traces on such devices, electromagnetic fields are generated around the traces. These fields may interfere with the operations of the devices, resulting in system failures, device malfunctions, link or synchronization failures, slower negotiated link speeds, etc.
In the situation of a device being powered on from a powered-off state (or returning from a power reset), a power good (“PGood”) signal may delay initialization of internal logic and functionality until stability has been reached. Further, in addition to the assertion of PGood to indicate power stability, some systems also add a delay module to cause further delay between the assertion of PGood and the de-assertion of a system reset signal, to further gate off internal logic; such a delay module may be used to ensure that when system reset is de-asserted and devices' functionalities are enabled, the devices are already in a stable state.
Various techniques relating to initial power-on are described in the PCI Express® Base Specification Revision 3.1a, published Dec. 7, 2015 (hereinafter, PCIe Base Specification), which is hereby incorporated by reference in its entirety.
Unlike when the system or device is first powered on, however, exiting from a low-power state typically does not benefit from the protection of the PGood signal or any delay modules. The return from a low-power state to a full-power state may result in a relative increase in crosstalk levels, and hence a relative decrease in the operating signal-to-noise ratio. During this time period, the system is considered to be in an “unstable period”. The high cross-talk and low signal-to-noise ratio affect the operation of nearby conductors, including differential signal pairs, which may have detrimental effects either in the form of data transmission errors or even collapse of the transmission system. In some cases, a device may attempt to negotiate a communications link during the “unstable period” and be only partially successful, with the result that the communications link may not operate at full speed. (For example, a PCIe ×8 device might only negotiate to operate at ×4 speeds, etc.)
Thus in general, when a device has been in a low-power state (such as an L2 state or an L3 state) and is returned to full power, there is typically no assurance that the device will reach a stable state before negotiation of a communication link is attempted. This can cause various adverse effects.
This disclosure provides techniques that may be employed to mitigate instabilities in these and other situations.
It should be noted that the discussion of a technique in the Background section of this disclosure does not constitute an admission of prior-art status. No such admissions are made herein, unless clearly and unambiguously identified as such.